1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and in particular to a semiconductor memory device having a multi-valued memory cell that stores a plurality of bits.
2. Description of the Prior Art
As means to realize a non-volatile semiconductor memory device, a technology using a multi-valued memory cell memorizing information with bits is known. In such a semiconductor memory device, threshold values for the multi-valued memory cell are set into multi-steps, and for example, when threshold values are set into four steps, four kinds of information, that is, 2-bit information will be stored in a single multi-valued memory cell.
Accordingly, a memory capacity of the same quantity as a normal semiconductor memory device, which can only store one-bit information, will become obtainable with a half cells of the above-described semiconductor memory device. Configuration and read-out of such a conventional semiconductor memory device will be described as follows with reference to drawings.
FIG. 6 is a block diagram showing a configuration of a conventional non-volatile semiconductor memory device. The semiconductor memory device in FIG. 6 comprises a memory cell array in which multi-valued memory transistors are disposed configuring a matrix. This memory array is classified into a cell plate L and a cell plate R, and further the cell plate L is classified into a cell plate L0 corresponding with an even address and a cell plate L1 corresponding with an odd address while the cell plate R is classified into a cell plate R0 corresponding to an even address and a cell plate R1 corresponding with an odd address.
Memory cell transistors ML0, ML1, MR0, and MR1 are respectively set at any one of threshold values among four kinds of threshold values VT0, VT1, VT2, and VT3 (but, VT0&lt;VT1&lt;VT2&lt;VT3). Accordingly, two-bit information will be stored at the memory cell transistors ML0, ML1, MR0, and MR1 respectively.
A row decoder 12 selects respectively one among a plurality of word lines WL and among word lines WR in accordance with an address signal inputted from outside.
A column decoder 13 controls column selectors 14L0, 14L1, 14R0, and 14R1 based on input address signals. A column selector 14L0 selects one among a plurality of bit line BL0, a column selector 14L1 selects one among a plurality of bit line BL1, a column selector 14R0 selects one among a plurality of bit line BR0, and a column selector 14R1 selects one among a plurality of bit line BR1.
Sense amplifiers 15L0, 15L1, 15R0, and 15R1 amplify outputs from column selectors 14L0, 14L1, 14R0, and 14R1.
Here, the row decoder 12 applies three-stage word-line voltage as shown in FIG. 7 to selected word-lines WL and WR in order to read out information of memory cell transistors ML0, ML1, MR0, and MR1. In FIG. 7, a mid-potential between the threshold values VT0 and VT1 is determined as a word 1, a mid-potential between the threshold values VT1 and VT2 is determined as a word 2, and a mid-potential between the threshold values VT2 and VT3 is determined as a word 3.
This will serve to sequentially cause data D1 corresponding with the potential of the word 1, D2 corresponding with the potential of the word 2, and D3 corresponding with the potential of the word 3 to appear at outputs of the sense amplifiers 15L0, 15L1, 15R0, and 15R1.
Latch circuits 16L0a, 16L1a, 16R0a, and 16R1a are circuits to maintain the data D1, latch circuits 16L0b, 16L1b, 16R0b, and 16R1b are circuits to maintain the data D2, latch circuits 16L0c, 16L1c, 16R0c, and 16R1c are circuits to maintain the data D3.
A binary conversion circuit 17L0 implements exclusive OR operation on the output data D3 of output data D1 of the latch circuit 16L0a and output data D3 of the latch circuit 16L0c, outputs its result as high order data HL0, and outputs output data D2 of the latch circuit 16L0b as low order data LL0.
A binary conversion circuit 17L1 implements exclusive OR operation on the output data D3 of output data D1 of the latch circuit 16L1a and output data D3 of the latch circuit 16L1c, outputs its result as high order data HL1 and outputs output data D2 of the latch circuit 16L1b as low order data LL1.
The binary conversion circuit 17R0 implements exclusive OR operation on the output data D1 of the latch circuit 16R0a and output data D3 of the latch circuit 16R0c, outputs its result as high order data HR0 and outputs output data D2 of the latch circuit 16R0b as low order data LR0.
In addition, the binary conversion circuit 17R1 implements exclusive OR operation on the output data D1 of the latch circuit 16R1a and output data D3 of the latch circuit 16R1c, outputs its result as high order data HR1 and outputs output data D2 of the latch circuit 16R1b as low order data LR1.
The output data conversion circuits 18L and 18R select either one of input data in accordance with an input address signal so as to output it as output data OUTL and OUTR.
A conventional semiconductor memory device having a multi-valued memory cell applies word-line voltage as in FIG. 7 to a memory cell transistor selected with the row decoder 12, the column decoder 13 and the column selectors 14L0, 14L1, 14R0, and 14R1 so as to read out data D1 to D3 sequentially and output high order data or low order data out of obtained two bits. That is, regardless whether the high order data or the low order data are read out, the order of variation of word-line voltage always remains same. Therefore, when high order data are appointed to be read out, unnecessary data D2 will be read out while unnecessary data D1 and D3 will be read out when low order data are appointed to be read out.
As described above, the conventional semiconductor memory device having a multi-valued memory cell, which varies the word-line voltage into multiple stages, has a problem that it requires longer read-out time than semiconductor memory device which is not a multi-valued one.